#ifndef _CSP_MACROS_H_ 
#define _CSP_MACROS_H_

/* We round up the so we don't have half a cacheline. 
 * This only works for 64bit arch.! */
#define PCB_PTRS_SIZE (sizeof(ea_addr_t)*(MAX_SPU_SLOTS + (MAX_SPU_SLOTS % 2)))


/* DMA completion flags */
//#define PCB_DMA_COMPLETION 		0x0BFBFBFBFBFB
#define PROCESS_DMA_COMPLETION 	0xAA


/* Max number of procs a spe-process can use in a parallel-call */
#define SILLY_MAGIC_NUMBER 1024

#define LOW32( _64bit ) ((uint32_t) _64bit)
#define HIGH32( _64bit ) ((uint64_t)_64bit >> 32)
#define EA_ADDR( _high32, _low32 ) ( (ea_addr_t) ((uint64_t) _high32 << 32) + _low32  )

#define CEIL_16( _int ) (((_int) + (16-1)) & ~(16-1))

#define NCALLEESAVES 48

#define VOLATILEREGISTERS 3

#define MAX_SPU_SLOTS 2

#define _16KB 16384

#define DMA_LIST_SIZE( bytes_total ) ( ((bytes_total)/_16KB) + (((bytes_total)%_16KB) != 0) )


#define MSG_CMD( msg )   (0xFFFF0000 & msg)
#define MSG_STATE( msg ) (0x0000F000 & msg)
#define MSG_OPT( msg )   (0x00000FFF & msg)

#define SAVE_PROC_AREA_SIZE( process_data_struct ) \
	( ((process_data_struct).stack_start - \
	  ((process_data_struct).vaddr + (process_data_struct).exec_size) * sizeof(char)) + \
	  VOLATILEREGISTERS * sizeof(qword) )

#define SAVE_REG_AREA( process_data_struct ) \
	( (process_data_struct).ea_store )

#define SAVE_BSS_AREA( process_data_struct ) \
	( (process_data_struct).ea_store+ (VOLATILEREGISTERS * sizeof(qword)) )

#define SAVE_STACK_AREA( process_data_struct ) \
	( ((process_data_struct).ea_store + (SAVE_PROC_AREA_SIZE(process_data_struct))) - (process_data_struct).stack_size )

#define LS_ADDR_IN_EASTORE( _pcb, _ls_addr) \
	(((_pcb)->ea_store + sizeof(qword)*VOLATILEREGISTERS) + \
	( (_ls_addr) - ((_pcb)->vaddr + (_pcb)->exec_size)));



#endif
